1. Field of the Invention
This invention relates to processes of manufacture of integrated circuit chips and more particularly to automatic control of production in an integrated circuit manufacturing process.
2. Description of Related Art
In a Job shop factory there are basically two types of production decisions required. The first type of decision to be made pertains to dispatching. The second type of decision to be made relates to the wafer release policy. In the past, both the dispatching decision and the wafer release policy were negotiated and handled separately in different, independent factory management centers. In such a conventional factory, dispatching decisions are carried out at each and every work center in the factory. Those dispatching decisions depend upon the status of the Work In Process (WIP), since there can be problems of unpredictable events such as machine breakdown, machine delay and scrapped work product. That is to say that the status of WIP varies based upon the quantity of product to be released and the status of equipment.
There are many methods of dispatching WIP which have been used in the past. Such methods of dispatching WIP include FIFO (First In First Out,) LBFS (Last Buffer First Service,) EDD (Earliest Due Date,) SLACK (Remaining Cycle Time--Remaining Process Time.), CR (Critical Ratio,) LDD (Local Due Date,) and MQT (Maximum Queue Time,) . . . and so on. All of the popular dispatching rules do not consider or include the wafer release policy being employed in the factory. Those prior art systems are based solely upon using the WIP status to dispatch work at a predicted due date based upon the pessimistic view that popular dispatching rules do not take care of WIP dispatching and wafer release to use WIP (Work In Process) management by using such popular dispatching rules.
U.S. Pat. No. 5,219,765 of Yoshida et al "Method for Manufacturing a Semiconductor Device Including Wafer Aging, Probe Inspection, and Feeding Back the Results of the Inspection to the Device Fabrication Process" describes a method for manufacturing semiconductor devices including tests from which information is fed back for fabrication process improvement.
U.S. Pat. No. 5,240,866 of Friedman et al "Method for Characterizing Failed Circuits on Semiconductor Wafers" shows a method for characterizing failed circuits on semiconductor wafers.
U.S. Pat. No. 5,210,041 of Kobayashi et al "Process for Manufacturing Semiconductor Integrated Circuit Device" shows computer control of testing/feedback in a chip manufacturing process control system.